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an important notice at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. advance information for pre-production products; subject to change without notice. TMP117 snosd82 ? june 2018 TMP117x high-accuracy, low-power, digital temperature sensor with smbus ? - and i 2 c-compatible interface 1 1 features 1 ? TMP117 high accuracy temperature sensor ? 0.1 c (maximum) from 25 c to +50 c ? 0.2 c (maximum) from ? 40 c to +125 c ? 0.3 c (maximum) from ? 55 c to +150 c ? TMP117m medical temperature sensor ? 0.1 c (maximum) from 30 c to +45 c ? TMP117n industrial temperature sensor ? 0.2 c (maximum) from ? 40 c to +125 c ? temperature operating range: ? 55 c to +150 c ? low power consumption: ? 3.5- a, 1-hz conversion cycle ? 250-na shutdown current ? supply range: 1.8 v to 5.5 v ? 16-bit resolution: 0.0078 c (1 lsb) ? programmable temperature alert limits ? digital offset for system correction ? general-purpose eeprom: 48 bits ? nist traceability ? smbus ? , i 2 c interface compatibility 2 applications ? medical grade: meets astm e1112 and iso 80601-2-56 ? environmental monitoring and thermostats ? wearables ? asset tracking and cold chain ? gas meters and heat meters ? test and measurement ? rtds replacement: pt100, pt500, pt1000 ? cold-junction compensation of thermocouples spacer 3 description the TMP117 is a high-precision digital temperature sensor. it is designed to exceed astm e1112 requirements for electronic patient thermometers. the TMP117 provides a 16-bit temperature result with a resolution of 0.0078 c and an accuracy of up to 0.1 c across the temperature range of 25 c to 50 c with no calibration. the TMP117 is i 2 c- and smbus ? -interface compatible, has programmable alert functionality, and can support up to four devices on a single bus. integrated eeprom is included for device programming with an additional 48-bits memory available for general use. the low power consumption of the TMP117 minimizes the impact of self-heating on measurement accuracy. the TMP117 operates from 1.8 v to 5.5 v and typically consumes 3.5 a. for non-medical applications, the TMP117 can serve as a single chip digital alternative to a platinum rtd. with an accuracy of 0.2 c accuracy from ? 55 c to 150 c, the TMP117 offers comparable if not better accuracy than can be achieved with a class a rtd, while only using a fraction of the power of the power typically needed for a pt100 rtd. the TMP117 simplifies the design effort by removing many of the complexities of rtds such as precision references, matched traces, complicated algorithms, and calibration. the TMP117 units are 100% tested on a production setup that is nist traceable and verified with equipment that is calibrated to iso/iec 17025 accredited standards. device information (1) part number package body size (nom) TMP117 wson (6) 2.00 mm 2.00 mm dsbga (6) 1.00 mm 1.60 mm (1) for all available packages, see the package option addendum at the end of the data sheet. functional block diagram temperature accuracy adc oscillator register bank serial interface control logic add0 scl sda gnd v+ alert copyright ? 2017, texas instruments incorporated eeprom temperature sensor circuitry internal thermal bjt temperature ( q c) temperature error ( q c) -55 -25 5 35 65 95 125 150 -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 d000 average avg r 3 v min/max limit advance information technical documents support &community ordernow productfolder tools & software
2 TMP117 snosd82 ? june 2018 www.ti.com product folder links: TMP117 submit documentation feedback copyright ? 2018, texas instruments incorporated table of contents 1 features .................................................................. 1 2 applications ........................................................... 1 3 description ............................................................. 1 4 revision history ..................................................... 2 5 pin configuration and functions ......................... 3 6 specifications ......................................................... 4 6.1 absolute maximum ratings ...................................... 4 6.2 esd ratings .............................................................. 4 6.3 recommended operating conditions ....................... 4 6.4 thermal information .................................................. 4 6.5 electrical characteristics ........................................... 4 6.6 switching characteristics .......................................... 5 6.7 two-wire interface timing ........................................ 6 6.8 typical characteristics .............................................. 7 7 detailed description .............................................. 9 7.1 overview ................................................................... 9 7.2 functional block diagrams ....................................... 9 7.3 feature description ................................................... 9 7.4 device functional modes ........................................ 11 7.5 programming ........................................................... 15 7.6 registers map ......................................................... 22 8 application and implementation ........................ 31 8.1 application information ............................................ 31 9 power supply recommendations ...................... 36 10 layout ................................................................... 36 10.1 layout guidelines ................................................. 36 10.2 layout example .................................................... 37 11 device and documentation support ................. 38 11.1 documentation support ....................................... 38 11.2 receiving notification of documentation updates 38 11.3 community resources .......................................... 38 11.4 trademarks ........................................................... 38 11.5 electrostatic discharge caution ............................ 38 11.6 glossary ................................................................ 38 12 mechanical, packaging, and orderable information ........................................................... 38 4 revision history note: page numbers for previous revisions may differ from page numbers in the current version. date revision notes june 2018 * initial release. advance information
3 TMP117 www.ti.com snosd82 ? june 2018 product folder links: TMP117 submit documentation feedback copyright ? 2018, texas instruments incorporated 5 pin configuration and functions drv package 6-pin wson top view yff package 6-pin dsbga top view pin functions pin type description name wson dsbga add0 4 c1 i address select. connect to gnd, v+, sda, or scl. alert 3 c2 o overtemperature alert or data-ready signal. open-drain output; requires a pullup resistor. gnd 2 b2 ? ground scl 1 a2 i serial clock sda 6 a1 i/o serial data. open-drain output; requires a pullup resistor. v+ 5 b1 i supply voltage: 1.8 v to 5.5 v sdav+ add0 65 4 scl gnd alert 12 3 thermal pad advance information 1 2 a b c not to scale sda scl v+ gnd add0 alert
4 TMP117 snosd82 ? june 2018 www.ti.com product folder links: TMP117 submit documentation feedback copyright ? 2018, texas instruments incorporated 6 specifications 6.1 absolute maximum ratings min max unit supply voltage v+ ? 0.3 6 v voltage at scl, sda, alert and add0 ? 0.3 6 v operating junction temperature, t j ? 55 150 c storage temperature, t stg ? 65 150 c (1) jedec document jep155 states that 500-v hbm allows safe manufacturing with a standard esd control process. (2) jedec document jep157 states that 250-v cdm allows safe manufacturing with a standard esd control process. 6.2 esd ratings value unit v (esd) electrostatic discharge human-body model (hbm), per ansi/esda/jedec js-001 (1) 2000 v charged-device model (cdm), per jedec specification jesd22- c101 (2) 1000 6.3 recommended operating conditions min nom max unit v+ supply voltage 1.8 3.3 5.5 v t a operating free-air temperature ? 55 150 c (1) for more information about traditional and new thermal metrics, see the ic package thermal metrics application report, spra953 . 6.4 thermal information thermal metric (1) tmp116 unit drv (wson) 6 pins r ja junction-to-ambient thermal resistance 68.7 c/w r jc(top) junction-to-case (top) thermal resistance 70.3 c/w r jc(bot) junction-to-case (bottom) thermal resistance 9.5 c/w r jb junction-to-board thermal resistance 38.3 c/w jt junction-to-top characterization parameter 1.7 c/w jb junction-to-board characterization parameter 38.6 c/w (1) v+ = 3.3 v, 8 averages, 1hz sampling (2) repeatability is the ability to reproduce a reading when the measured temperature is applied consecutively, under the same conditions. (3) long term stability is determined using accelerated operational life testing at a junction temperature of 150 c. 6.5 electrical characteristics minimum and maximum specifications are over -55 c to 150 c and v+ = 1.8 v to 5.5 v (unless otherwise noted); typical specifications are at t a = 25 c and v+ = 3.3 v. parameter test conditions min typ max unit temperature to digital converter temperature accuracy (1) TMP117m 30 c to 45 c -0.1 0.05 0.1 c 0 c to 85 c -0.2 0.1 0.2 TMP117 25 c to 50 c -0.1 0.05 0.1 -55 c to 150 c -0.2 0.1 0.2 TMP117n -55 c to 150 c -0.2 0.1 0.2 dc power supply sensitivity one-shot mode, 8 averages, t a = +25 c 10 m c/v temperature resolution (lsb) 7.8125 m c repeatability (2) (1) 1 lsb long-term stability and drift 300 hours at 150 c (3) 0.02 c advance information
5 TMP117 www.ti.com snosd82 ? june 2018 product folder links: TMP117 submit documentation feedback copyright ? 2018, texas instruments incorporated electrical characteristics (continued) minimum and maximum specifications are over -55 c to 150 c and v+ = 1.8 v to 5.5 v (unless otherwise noted); typical specifications are at t a = 25 c and v+ = 3.3 v. parameter test conditions min typ max unit (4) hysteresis is defined as the ability to reproduce a temperature reading as the temperature varies from room hot room cold room. the temperatures used for this test are -40 c, 25 c, and 150 c. (5) quiescent current between conversions temperature cycling and hysteresis (4) 8 averages 1 lsb digital input/output input capacitance 4 pf v ih input logic high level 0.7 (v+) v v il input logic low level 0.3 (v+) v i in input current -0.1 0.1 a v ol s sda output logic low level i ol = -3 ma 0 0.4 v v ol a alert output logic low level i ol = -3 ma 0 0.4 v power supply i q quiescent current active conversion, serial bus inactive 135 220 a i q quiescent current duty cycle 1 hz, averaging mode off, serial bus inactive 3.5 4.5 a duty cycle 1 hz, 8 avgerages mode, serial bus inactive 16 22 duty cycle 1 hz, averaging mode off, serial bus active, scl frequency = 400 khz 15 i sb stanby current (5) serial bus inactive, scl and sda = v+ 1.25 2.1 a i sd shutdown current serial bus inactive, scl and sda = v+, 25 c 0.15 0.5 a serial bus inactive, scl and sda = v+, 125 c 4 a serial bus active, scl frequency = 400 khz 17 a i ee eeprom write quiescent current adc conversion off; serial bus inactive 240 a v por power-on-reset threshold voltage supply going up 1.6 v brownout detect supply going down 1.1 v reset time time required by device to reset 1.5 ms conversion time one-shot mode 13.5 15.5 17 ms 6.6 switching characteristics minimum and maximum specifications are over -55 c to 150 c and v+ = 1.8 v to 5.5 v (unless otherwise noted) typical specifications are at t a = 25 c and v+ = 3.3 v. parameter test conditions min typ max unit eeprom programming time 7 ms number of writes 1,000 50,000 times data retention time 10 100 years advance information
6 TMP117 snosd82 ? june 2018 www.ti.com product folder links: TMP117 submit documentation feedback copyright ? 2018, texas instruments incorporated (1) the master and device have the same v+ value. values are based on statistical analysis of samples tested during initial release. (2) the maximum t hd;dat could be 0.9 s for fast-mode, and is less than the maximum t vd;dat by a transition time. (3) t vd;data = time for data signal from scl " low " to sda output ( " high " to " low " , depending on which is worse). 6.7 two-wire interface timing minimum and maximum specifications are over ? 55 c to 150 c and v+ = 1.8 v to 5.5 v (unless otherwise noted) (1) fast-mode unit min max f scl scl operating frequency 1 400 khz t buf bus free time between stop and start conditions 1300 ns t hd;sta hold time after repeated strat condition. after this period, the first clock is generated (2) 600 ns t su;sta repeated start condition setup time 600 ns t su;sto stop condition setup time 600 ns t hd;dat data hold time 0 ns t vd;dat data valid time (3) 0.9 s t su;dat data setup time 100 ns t low scl clock low period 1300 ns t high scl clock high period 600 ns t f ? sda data fall time 20 (v+ /5.5) 300 ns t f , t r ? scl clock fall and rise time 300 ns t r rise time for scl 100 khz 1000 ns serial bus timeout (sda bus released if there is no clock) 20 40 ms figure 1. two-wire timing diagram v ih v il scl p s v ih v il sda t buf t hd;sta t low t r t hd;dat t high t f t su;dat t su;sta t su;sto p s t vd;dat advance information
7 TMP117 www.ti.com snosd82 ? june 2018 product folder links: TMP117 submit documentation feedback copyright ? 2018, texas instruments incorporated 6.8 typical characteristics at t a = 25 c, v+ = 3.3 v, and measurement taken in oil bath (unless otherwise noted) 1-hz conversion cycle, 8 averages mode figure 2. temperature error vs temperature figure 3. temperature error vs supply voltage continuous conversion, no conversion cycle in still air figure 4. temperature error vs supply voltage figure 5. data reading distribution over supply voltage (no averaging) figure 6. data reading distribution over temperature (no averaging) serial bus inactive figure 7. quiescent current in shutdown mode supply voltage (v) temperature error (m q c) 1.5 2 2.5 3 3.5 4 -60 -50 -40 -30 -20 -10 0 10 20 30 40 50 d002 data distribution (lsb) population (%) 0 10 20 30 40 50 60 70 80 -4 -3 -2 -1 0 1 2 3 4 v = +1.9 v, st. dev = 0.91 v = +3.3 v, st. dev = 1.01 v = +5 v, st. dev = 0.96 data distribution (lsb) population (%) 0 10 20 30 40 50 60 70 80 -4 -3 -2 -1 0 1 2 3 4 -40 c, st. dev = 1.12 25 c, st. dev = 1.01 125 c, st. dev = 1.05 temperature ( q c) temperature error ( q c) -55 -25 5 35 65 95 125 150 -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 d000 average avg r 3 v min/max limit 0 1 2 3 4 5 6 7 8 9 10 C50 C25 0 25 50 75 100 125 current (a) temperature (c) 3.3 v 1.9 v advance information supply voltage (v) temperature error (m q c) 1.5 2 2.5 3 3.5 4 -40 -30 -20 -10 0 10 20 30 40 50 60 70 d001 1 shot, no conv cycles 8 averages, conv cycle = 1 s 1 conversion, conv cycle = 500 ms
8 TMP117 snosd82 ? june 2018 www.ti.com product folder links: TMP117 submit documentation feedback copyright ? 2018, texas instruments incorporated typical characteristics (continued) at t a = 25 c, v+ = 3.3 v, and measurement taken in oil bath (unless otherwise noted) serial bus inactive figure 8. quiescent current in standby mode scl, sda, add0 pins are constantly clocked figure 9. quiescent current in shutdown mode normalized to 25 c and v+ = 3.3 v figure 10. active conversion time vs temperature figure 11. alert pin output voltage vs pin sink current input voltage of scl, sda, or add0 pin figure 12. supply current vs input cell voltage bus frequency (mhz) current ( p a) 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 0 5 10 15 20 25 30 35 40 45 d010 3.3 v 1.9 v advance information 0 1 2 3 4 5 6 7 8 9 10 C50 C25 0 25 50 75 100 125 current (a) temperature (c) 3.3 v 1.9 v temperature (c) active conversion time change -55 -25 5 35 65 95 125 150 -5 -4 -3 -2 -1 0 1 2 3 4 5 1.9 v 3.3 v percentage (%) sink current (ma) vout (v) 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 d022 1.9 v 2 v 3.3 v vin / v+ (%) current ( p a) 0 10 20 30 40 50 60 70 80 90 100 0 50 100 150 200 250 300 d021 3.3 v 2 v
9 TMP117 www.ti.com snosd82 ? june 2018 product folder links: TMP117 submit documentation feedback copyright ? 2018, texas instruments incorporated 7 detailed description 7.1 overview the TMP117 is a digital output temperature sensor that is optimal for thermal-management and thermal- protection applications. the TMP117 is two-wire, smbus, and i 2 c interface-compatible. the device is specified over an operating temperature range of ? 55 c to +125 c. figure 13 shows a block diagram of the TMP117. 7.2 functional block diagrams figure 13. internal block diagram 7.3 feature description 7.3.1 power up after the supply voltage reaches within the operating range, the device requires 1.5 ms to power up before conversions begin. the device can be programmed to start up in shutdown mode as well. see the eeprom programming section for more information. the temperature register reads ? 256 c before the first conversion. 7.3.2 temperature result and limits at the end of every conversion, the device updates the temperature register with the conversion result. the data reading in the result register is in two's complement format, has a data width of 16 bits, and a resolution of 7.8125 m c. table 1 shows multiple examples of possible binary data that can be read from the temperature result register and the corresponding hexadecimal and decimal equivalents. the TMP117 also has alert status flags and alert pin functionality that use the temperature limits stored in the low limit register and high limit register . the same data format used for the temperature result register can be used for data that are written to the high and low limit registers. adc oscillator register bank serial interface control logic add0 scl sda gnd v+ alert copyright ? 2017, texas instruments incorporated eeprom temperature sensor circuitry internal thermal bjt advance information
10 TMP117 snosd82 ? june 2018 www.ti.com product folder links: TMP117 submit documentation feedback copyright ? 2018, texas instruments incorporated feature description (continued) table 1. 16-bit temperature data format temperature ( c) temperature register value (0.0078125 c resolution) binary hex ? 256 1000 0000 0000 0000 8000 ? 25 1111 0011 1000 0000 f380 ? 0.1250 1111 1111 1111 0000 fff0 ? 0.0078125 1111 1111 1111 1111 ffff 0 0000 0000 0000 0000 0000 0.0078125 0000 0000 0000 0001 0001 0.1250 0000 0000 0001 0000 0010 1 0000 0000 1000 0000 0080 25 0000 1100 1000 0000 0c80 100 0011 0010 0000 0000 3200 255.9921 0111 1111 1111 1111 7fff advance information
11 TMP117 www.ti.com snosd82 ? june 2018 product folder links: TMP117 submit documentation feedback copyright ? 2018, texas instruments incorporated 7.4 device functional modes 7.4.1 temperature conversions the TMP117 can be configured to operate in various conversion modes by using the mod[1:0] bits. these modes provide flexibility to operate the device in the most power efficient way necessary for the intended application. 7.4.1.1 conversion cycle when the device is operating in continuous conversion mode (see the continuous conversion mode (cc) section), every conversion cycle consists of an active conversion period followed by a standby period. the device typically consumes 135 a during active conversion, and the device typically consumes 1.25 a during the low- power standby period, as indicated in table 1 . figure 14 shows a representative current consumption profile of a conversion cycle. the duration of the active conversion period and standby period can be configured using the conv[2:0] and avg[1:0] bits in the configuration register , thereby allowing the average current consumption of the device to be optimized based on the application requirements. changing the conversion cycle period also affects the temperature result update rate because the temperature result register is updated at the end of every conversion. figure 14. conversion cycle timing diagram 7.4.1.2 averaging users can configure the device to report the average of multiple temperature conversions with the avg[1:0] bits to improve noise in the conversion results. when the TMP117 is configured to perform averaging, the device executes the configured number of conversions. the device accumulates those conversion results and reports the average of all the collected results at the end of the process. as shown in the noise histograms of figure 6 and , the temperature result output has a repeatability of approximately 3 lsbs when there is no averaging and 1 lsb when the device is configured to perform eight averages. as shown in figure 15 , engineer can achieve this improvement in noise performance with an increase in the active conversion time in a conversion cycle as a trade-off. note that this outcome will increase the average active current consumption. for example, a single active conversion typically takes 15.5 ms, so if the device is configured to report an average of eight conversions, then the active conversion time is 124 ms (15.5 ms 8). use equation 1 to factor in this increase in active conversion time to accurately calculate the average current consumption of the device. the average current consumption of the device can be decreased by increasing the amount of time the device spends in standby period as compared to active conversion. on reset, the device is configured to report an average of eight conversions with a conversion cycle time of 1 second. figure 15. averaging timing diagram advance information 1 second 15.5 ms 124 ms, 8 conv standby data_ready i c temperature register read 2 8 averages, 1-hz cc standby 15.5 ms 1 conversion cycle 15.5 ms start-up start of conversion active conversion
12 TMP117 snosd82 ? june 2018 www.ti.com product folder links: TMP117 submit documentation feedback copyright ? 2018, texas instruments incorporated device functional modes (continued) use equation 1 to calculate the average current consumption of the device in continuous mode. (1) 7.4.1.3 continuous conversion mode (cc) when the mod[1:0] bits are set to 00 in the configuration register , the device operates in continuous conversion mode. the device continuously performs temperature conversions in this mode, as shown in figure 14 , and updates the temperature result register at the end of every conversion. as described in the conversion cycle section, every conversion cycle consists of an active conversion period followed by a standby period whose duration can be configured using the conv and avg bits in the configuration register based on the temperature accuracy, power consumption, and temperature update rate trade-offs of the application that the device is used in. at the end of a conversion, the data_ready flag in the configuration register is set. the user can read the configuration register or the temperature result register to clear the data_ready flag. therefore, the data_ready flag can be used to determine when the conversion completes so that an external controller can synchronize reading the result register with conversion result updates. the user can set the dr/nalert_en bit in the configuration register to monitor the state of the data_ready flag on the alert pin. 7.4.1.4 shutdown mode (sd) when the mod[1:0] bits are set to 01 in the configuration register , the device instantly aborts the currently running conversion and enters a low-power shutdown mode. in this mode, the device powers down all active circuitry and can be used in conjunction with the os mode to perform temperature conversions. in sd mode, the device typically consumes only 250 na, which makes the TMP117 suitable for battery-operated systems and other low-power consumption applications. 7.4.1.5 one-shot mode (os) when mod[1:0] bits are set to 11 in the configuration register to run a single conversion, referred to as a one- shot conversion. after the device completes a one-shot conversion, the device returns to the low-power shutdown mode. a one-shot conversion cycle only consists of active conversion time and no standby period, unlike cc mode. thus, the duration of a one-shot conversion is only affected by the avg bit settings. the conv bits do not affect the duration of a one-shot conversion. figure 16 shows a timing diagram for this mode with an avg setting of 00. at the end of a one-shot conversion, the data_ready flag in the configuration register is set. the data_ready flag can thus be used to determine when the conversion completes. the user can perform an i 2 c read on the configuration register or temperature result register to clear the data_ready flag. the user can also set the dr/nalert_en bit in the configuration register to monitor the state of the data_ready flag on the alert pin. figure 16. one-shot timing diagram 7.4.2 therm and alert functions the built-in therm and alert functions of the TMP117 can alert the user if the temperature has crossed a certain temperature limit or if the device is within a certain temperature range. at the end of every conversion, the TMP117 compares the converted temperature result to the values stored in the low limit register and high limit register . the device then either sets or clears the corresponding status flags in the configuration register, as described in this section. advance information shutdown 15.5 ms(one-shot conversion) (active current consumption active conversion time) + (standby c urrent consumption standby time) conversion cycle time u u
13 TMP117 www.ti.com snosd82 ? june 2018 product folder links: TMP117 submit documentation feedback copyright ? 2018, texas instruments incorporated device functional modes (continued) 7.4.2.1 alert mode when the t/na bit in the configuration register is set to 0, the device is in alert mode. in this mode, the device compares the conversion result at the end of every conversion with the values in the low limit register and high limit register . if the temperature result exceeds the value in the high limit register, the high_alert status flag in the configuration register is set. on the other hand, if the temperature result is lower than the value in the low limit register, the low_alert status flag in the configuration register is set. as shown in figure 17 , the user can run an i 2 c read transaction on the configuration register to clear the status flags in alert mode. when a user configures the device in alert mode, it affects the behaviour of the alert pin. the device asserts the alert pin in this mode when either the high_alert or the low_alert status flag is set, as shown in figure 17 . the user can either run an i 2 c read of the configuration register (which also clears the status flags) or run an smbus alert response command (see the smbus alert function section) to deassert the alert pin. the polarity of the alert pin can be changed by using the pol bit setting in the configuration register. this mode effectively makes the device behave like a window limit detector. thus this mode can be used in applications where detecting if the temperature goes outside of the specified range is necessary. figure 17. alert mode timing diagram high limit low limit conversion completed high_alert status flag low_alert status flag configuration register i 2 c read alert pin (pol = 0) smbus alert response command actual temperature advance information
14 TMP117 snosd82 ? june 2018 www.ti.com product folder links: TMP117 submit documentation feedback copyright ? 2018, texas instruments incorporated device functional modes (continued) 7.4.2.2 therm mode when the t/na bit in the configuration register is set to 1 the device is in therm mode. in this mode, the device compares the conversion result at the end of every conversion with the values in the low limit register and high limit register and sets the high_alert status flag in the configuration register if the temperature exceeds the value in the high limit register. when set, the device clears the high_alert status flag if the conversion result goes below the value in the low limit register. thus, the difference between the high and low limits effectively acts like a hysteresis. in this mode, the low_alert status flag is disabled and always reads 0. unlike the alert mode, i 2 c reads of the configuration register do not affect the status bits. the high_alert status flag is only set or cleared at the end of conversions based on the value of the temperature result compared to the high and low limits. as in alert mode, configuring the device in therm mode also affects the behaviour of the alert pin. in this mode, the device asserts the alert pin if the high_alert status flag is set and deasserts the alert pin when the high_alert status flag is cleared. in therm mode, the alert pin cannot be cleared by performing an i 2 c read of the configuration register or by performing an smbus alert response command. as in alert mode, the polarity of the active state of the alert pin can be changed if the user adjusts the pol bit setting in the configuration register. thus, this mode effectively makes the device behave like a high-limit threshold detector. this mode can be used in applications where detecting if the temperature has gone above a desired threshold is necessary. figure 18 shows a timing diagram of this mode. figure 18. therm mode timing diagram high limit low limit conversion completed high_alert status flag alert pin (pol = 0) actual temperature advance information
15 TMP117 www.ti.com snosd82 ? june 2018 product folder links: TMP117 submit documentation feedback copyright ? 2018, texas instruments incorporated 7.5 programming 7.5.1 eeprom programming 7.5.1.1 eeprom overview the device has a user-programmable eeprom that can be used for two purposes: ? storing power-on-reset (por) values of the high limit register, low limit register, conversion cycle time, averaging mode, conversion mode (continuous or shutdown mode), alert function mode (alert or therm mode), and alert polarity ? storing four 16-bit locations for general-purpose use. see the eeprom[4:1] registers for more information. on reset, the device goes through a por sequence that loads the values programmed in the eeprom into the respective register map locations. this process takes approximately 1.5 ms. when the power-up sequence is complete, the device starts operating in accordance to the configuration parameters that are loaded from the eeprom. any i 2 c writes performed during this initial por period to the limit registers or the configuration register are ignored. i 2 c read transactions can still be performed with the device during the power-up period. while the por sequence is being executed, the eeprom_busy status flag in the eeprom unlock register is set. during production, the eeprom in the TMP117 is programmed with reset values as shown in table 3 . the programming the eeprom section describes how to change these values. a unique id is also programmed in the general-purpose eeprom locations during production. this unique id is used to support nist traceability. the TMP117 units are 100% tested on a production setup that is nist traceable and verified with equipment that is calibrated to iso/iec 17025 accredited standards. only reprogram the general-purpose eeprom[4:1] locations if nist traceability is not desired. 7.5.1.2 programming the eeprom to prevent accidental programming, the eeprom is locked by default. when locked, any i 2 c writes to the register map locations are performed only on the volatile registers and not on the eeprom. figure 19 illustrates a flow chart describing the eeprom programming sequence. to program the eeprom, first unlock the eeprom by setting the eun bit in the eeprom unlock register . after the eeprom is unlocked, any subsequent i 2 c writes to the register map locations program a corresponding non-volatile memory location in the eeprom. programming a single location typically takes 7 ms to complete and consumes 230 a. do not perform any i 2 c writes until programming is complete. during programming, the eeprom_busy flag is set. read this flag to monitor if the programming is complete. after programming the desired data, issue a general-call reset command to trigger a software reset. the programmed data from the eeprom are then loaded to the corresponding register map locations as part of the reset sequence. this command also clears the eun bit and automatically locks the eeprom to prevent any further accidental programming. avoid using the device to perform temperature conversions when the eeprom is unlocked. advance information
16 TMP117 snosd82 ? june 2018 www.ti.com product folder links: TMP117 submit documentation feedback copyright ? 2018, texas instruments incorporated programming (continued) figure 19. eeprom programming sequence start end set bit 15 of the eeprom unlock register to 1 to unlock write desired data to the register wait 7 ms general-call reset read programed registers to verify eeprom_busy = 0 (programming complete) eeprom_busy = 1 (still programming) read back eeprom_busy from eeprom unlock register program another location? yes no programming process advance information
17 TMP117 www.ti.com snosd82 ? june 2018 product folder links: TMP117 submit documentation feedback copyright ? 2018, texas instruments incorporated programming (continued) 7.5.2 pointer register figure 20 shows the internal register structure of the TMP117. the 8-bit pointer register of the device is used to address a given data register. the power-up reset value is 00. by default, the TMP117 reads the temperature on power-up. figure 20. internal register structures 7.5.3 i 2 c and smbus interface 7.5.3.1 serial interface the TMP117 operates as a slave device only on the two-wire, smbus and i 2 c interface-compatible bus. connections to the bus are made through the open-drain i/o lines and the sda and scl pins. the sda and scl pins feature integrated spike-suppression filters and schmitt triggers to minimize the effects of input spikes and bus noise. the device supports the transmission protocol for fast (1 khz to 400 khz) mode. register bytes are sent with the most significant byte first, followed by the least significant byte. 7.5.3.1.1 bus overview the device that initiates the transfer is called a master , and the devices controlled by the master are slaves . the bus must be controlled by a master device that generates the serial clock (scl), controls the bus access, and generates the start and stop conditions. to address a specific device, a start condition is initiated, indicated by pulling the data line (sda) from a high- to low-logic level when the scl pin is high. all slaves on the bus shift in the slave address byte on the rising edge of the clock, and the last bit indicates whether a read or write operation is intended. during the ninth clock pulse, the addressed slave generates an acknowledge and pulls the sda pin low to respond to the master. a data transfer is then initiated and sent over eight clock pulses followed by an acknowledge bit. during the data transfer, the sda pin must remain stable when the scl pin is high because any change in the sda pin when the scl pin is high is interpreted as a start or stop signal. when all data are transferred, the master generates a repeated start or stop condition indicated by pulling the sda pin from low to high when the scl pin is high. i/o control interface sclsda temperature register configuration register t low register eeprom1 to 4 pointer register t high register advance information
18 TMP117 snosd82 ? june 2018 www.ti.com product folder links: TMP117 submit documentation feedback copyright ? 2018, texas instruments incorporated programming (continued) 7.5.3.1.2 serial bus address to communicate with the TMP117, the master must first address slave devices through an address byte. the address byte has seven address bits and a read-write (r/w) bit that indicates the intent of executing a read or write operation. the TMP117 features an address pin to allow up to four devices to be addressed on a single bus. table 2 describes the pin logic levels used to properly connect up to four devices. x represents the read-write (r/ w) bit. table 2. address pin and slave addresses device two-wire address add0 pin connection 1001000x ground 1001001x v+ 1001010x sda 1001011x scl 7.5.3.1.3 writing and reading operation the user can write a register address to the pointer register to access a particular register on the TMP117. the value for the pointer register is the first byte transferred after the slave address byte with the r/ w bit low. every write operation to the TMP117 requires a value for the pointer register. when reading from the TMP117, the last value stored in the pointer register by a write operation is used to determine which register is read by a read operation. to change the register pointer for a read operation, a new value must be written to the pointer register. the user can issue an address byte with the r/ w bit low, followed by the pointer register byte, to write a new value for the pointer register. no additional data are required. the master can then generate a start condition and send the slave address byte with the r/ w bit high to initiate the read command. see figure 23 for details of this sequence. if repeated reads from the same register are desired, it is not necessary to send the pointer register bytes continuously because the TMP117 retains the pointer register value until the value is changed by the next write operation. register bytes are sent with the most significant byte first, followed by the least significant byte. 7.5.3.1.4 slave mode operations the TMP117 can operate as a slave receiver or slave transmitter. as a slave device, the TMP117 never drives the scl line. 7.5.3.1.4.1 slave receiver mode the first byte transmitted by the master is the slave address with the r/ w bit low. the TMP117 then acknowledges reception of a valid address. the next byte transmitted by the master is the pointer register. the TMP117 then acknowledges reception of the pointer register byte. the next byte or bytes are written to the register addressed by the pointer register. the TMP117 acknowledges reception of each data byte. the master can terminate data transfer by generating a start or stop condition. 7.5.3.1.4.2 slave transmitter mode the first byte transmitted by the master is the slave address with the r/ w bit high. the slave acknowledges reception of a valid slave address. the next byte is transmitted by the slave and is the most significant byte of the register indicated by the pointer register. the master acknowledges reception of the data byte. the next byte transmitted by the slave is the least significant byte. the master acknowledges reception of the data byte. the master can terminate data transfer by generating a not-acknowledge on reception of any data byte or by generating a start or stop condition. advance information
19 TMP117 www.ti.com snosd82 ? june 2018 product folder links: TMP117 submit documentation feedback copyright ? 2018, texas instruments incorporated 7.5.3.1.5 smbus alert function the TMP117 supports the smbus alert function. when the alert pin is connected to an smbus alert signal and a master senses that an alert condition is present, the master can send out an smbus alert command (0001 1001) to the bus. if the alert pin is active, the device acknowledges the smbus alert command and responds by returning the slave address on the sda line. the eighth bit (lsb) of the slave address byte indicates if the alert condition is caused by the temperature exceeding t (high) or falling below t (low) . the lsb is high if the temperature is greater than t (high) , or low if the temperature is less than t (low) . see figure 24 for details of this sequence. if multiple devices on the bus respond to the smbus alert command, arbitration during the slave address portion of the smbus alert command determines which device clears the alert status of that device. the device with the lowest two-wire address wins the arbitration. if the TMP117 wins the arbitration, the TMP117 alert pin becomes inactive at the completion of the smbus alert command. if the TMP117 loses the arbitration, the TMP117 alert pin remains active. 7.5.3.1.6 general-call reset function the TMP117 responds to a two-wire, general-call address (0000 000) if the eighth bit is 0. the device acknowledges the general-call address and responds to commands in the second byte. if the second byte is 0000 0110, the TMP117 internal registers are reset to power-up values. 7.5.3.1.7 timeout function the TMP117 resets the serial interface if the scl line is held low by the master or the sda line is held low by the TMP117 for 35 ms (typical) between a start and stop condition. the TMP117 releases the sda line if the scl pin is pulled low and waits for a start condition from the host controller. to avoid activating the timeout function, maintain a communication speed of at least 1 khz for the scl operating frequency. 7.5.3.1.8 timing diagrams the TMP117 is two-wire, smbus, and i 2 c interface-compatible. figure 21 to figure 25 show the various operations on the TMP117. parameters for figure 21 are defined in two-wire interface timing . bus definitions are: bus idle: both sda and scl lines remain high. start data transfer: a change in the state of the sda line from high to low when the scl line is high defines a start condition. each data transfer is initiated with a start condition. stop data transfer: a change in the state of the sda line from low to high when the scl line is high defines a stop condition. each data transfer is terminated with a repeated start or stop condition. data transfer: the number of data bytes transferred between a start and a stop condition is not limited and is determined by the master device. the TMP117 can also be used for single byte updates. to update only the ms byte, terminate the communication by issuing a start or stop communication on the bus. acknowledge: each receiving device, when addressed, is obliged to generate an acknowledge bit. a device that acknowledges must pull down the sda line during the acknowledge clock pulse in such a way that the sda line is stable low during the high period of the acknowledge clock pulse. the user must take setup and hold times into account. on a master receive, the termination of the data transfer can be signaled by the master generating a not-acknowledge (1) on the last byte transmitted by the slave. figure 21. two-wire timing diagram scl sda t (low) t rc t fc t (hdsta) t (hdsta) t (hddat) t (sudat) t (high) t (susta) t (susto) t (buf) s s p p t rd t fd advance information
20 TMP117 snosd82 ? june 2018 www.ti.com product folder links: TMP117 submit documentation feedback copyright ? 2018, texas instruments incorporated figure 22. write word command timing diagram figure 23. read word command timing diagram frame 3 two-wire slave address byte frame 4 data byte 1 read register start by master ack by device ack by master from device 1 9 1 9 ? ? sda (continued) scl (continued) sda (continued) scl (continued) 1 0 0 a1 a0 r/w d15 d14 d13 d12 d11 d10 d9 d8 frame 5 data byte 2 read register stop by master nack by master from device 1 9 d7 d6 d5 d4 d3 d2 d1 d0 0 frame 1 two-wire slave address byte frame 2 pointer register byte 1 start by master ack by device ack by device 1 9 1 9 sda scl 0 0 1 a1 a0 r/w 0 0 0 p3 p2 p1 p0 ? ? 1 0 0 advance information frame 1 two-wire slave address byte frame 2 pointer register byte frame 4 data byte 2 1 start by master ack by device ack by device ack by device stop by master 1 9 1 1 d7 d6 d5 d4 d3 d2 d1 d0 9 frame 3 data byte 1 ack by device 1 d15 sda (continued) scl (continued) d14 d13 d12 d11 d10 d9 d8 9 9 sda scl 0 0 1 a1 a0 r/w 0 0 0 0 p3 p2 p1 p0 ? ? 0
21 TMP117 www.ti.com snosd82 ? june 2018 product folder links: TMP117 submit documentation feedback copyright ? 2018, texas instruments incorporated figure 24. smbus alert timing diagram figure 25. general-call reset command timing diagram advance information frame 1 smbus alert response address byte frame 2 slave address from device start by master ack by device from device nack by master stop by master 1 9 1 9 sda scl alert 0 0 0 1 1 0 0 r/ w 1 0 0 1 status a1 (1) a0 (1) 0 start by master ack by device from master ack by device stop by master 1 9 1 9 sda scl 0 0 0 0 0 0 0 r/ w 0 0 0 0 0 1 1 0 frame 1 address byte frame 2 command byte 1
TMP117 snosd82 ? june 2018 www.ti.com 22 product folder links: TMP117 submit documentation feedback copyright ? 2018, texas instruments incorporated (1) this value is stored in electrically-erasable, programmable read-only memory (eeprom) during device manufacturing. the device reset value can be changed by writing the relevant code in the eeprom cells (see the eeprom overview section). 7.6 registers map table 3. register map address (hex) default value (hex) register data register name 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 00h 8000 t15 t14 t13 t12 t11 t10 t9 t8 t7 t6 t5 t4 t3 t2 t1 t0 temperature 01h 0220 (1) high_ alert low_ alert data_ ready eeprom _busy mod1 mod0 conv2 conv1 conv0 avg1 avg0 t/na pol dr/nalert _en soft_rest ? configuration 02h 6000 (1) h15 h14 h13 h12 h11 h10 h9 h8 h7 h6 h5 h4 h3 h2 h1 h0 high limit 03h 8000 (1) l15 l14 l13 l12 l11 l10 l9 l8 l7 l6 l5 l4 l3 l2 l1 l0 low limit 07h 0000 (1) d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 temperature offset 04h 0000 eun eeprom _ busy ? ? ? ? ? ? ? ? ? ? ? ? ? ? eeprom unlock 05h xxxx (1) d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 eeprom1 06h xxxx (1) d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 eeprom2 08h xxxx (1) d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 eeprom3 0fh x116 ? ? ? ? did11 did10 did9 did8 did7 did6 did5 did4 did3 did2 did1 did0 device ld advance information
23 TMP117 www.ti.com snosd82 ? june 2018 product folder links: TMP117 submit documentation feedback copyright ? 2018, texas instruments incorporated 7.6.1 register descriptions table 4. TMP117 access type codes access type code description r r read read-write r/w read, write, or both w w write - n value after reset or the default value 7.6.1.1 temperature register (address = 00h) [default reset = 8000h] this register is a 16-bit, read-only register that stores the output of the most recent conversion. one lsb equals 7.8125 m c. data are represented in binary two's complement format. following power-up or a general-call reset, the temperature register reads ? 256 c until the first conversion is complete. see the power up section for more information. figure 26. temperature register 15 14 13 12 11 10 9 8 t15 t14 t13 t12 t11 t10 t9 t8 r-1 r-0 r-0 r-0 r-0 r-0 r-0 r-0 7 6 5 4 3 2 1 0 t7 t6 t5 t4 t3 t2 t1 t0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 table 5. temperature register field descriptions bit field type reset description 15:0 t[15:0] r 8000h 16-bit, read-only register that stores the most recent temperature conversion results. advance information
24 TMP117 snosd82 ? june 2018 www.ti.com product folder links: TMP117 submit documentation feedback copyright ? 2018, texas instruments incorporated 7.6.1.2 configuration register (address = 01h) [default reset = 0220h] (1) the mod1 bit cannot be stored in eeprom. the device can only be programmed to start up in shutdown mode or continuous conversion mode. (2) these bits can be stored in eeprom. the factory setting for this register is 0220. figure 27. configuration register 15 14 13 12 11 10 9 8 high_alert low_alert data_ready eeprom_busy mod1 (1) mod0 (2) conv2 (2) conv1 (2) r-0 r-0 r-0 r-0 r/w-0 r/w-0 r/w-1 r/w-0 7 6 5 4 3 2 1 0 conv0 (2) avg1 (2) avg0 (2) t/na (2) pol (2) dr/alert (2) ? ? r/w-0 r/w-0 r/w-1 r/w-0 r/w-0 r/w-0 r-0 r-0 table 6. configuration register field descriptions bit field type reset description 15 high_alert r 0 alert mode: 1: set when the conversion result is higher than the high limit 0: cleared on read of configuration register therm mode: 1: set when the conversion result is higher than the therm limit 0: cleared when the conversion result is lower than the hysteresis 14 low_alert r 0 alert mode: 1: set when the conversion result is lower than the low limit 0: cleared when the configuration register is read therm mode: always set to 0 13 data_ready r 0 data ready flag. this flag indicates that the conversion is complete and the temperature register can be read. every time the temperature register or configuration register is read, this bit is cleared. this bit is set at the end of the next conversion when the temperature register is updated. data ready can be monitored on the alert pin by using bit 2 of the configuration register. 12 eeprom_busy r 0 eeprom busy flag. the value of the flag indicates that the eeprom is busy during programming or power-up. 11:10 mod[1:0] r/w 0 set conversion mode. 00: continuous conversion (cc) 01: shutdown (sd) 10: continuous conversion (read back = 00) 11: one-shot conversion (os) 9:7 conv[2:0] r/w 100 conversion cycle bit. see table 7 for the standby time between conversions. 6:5 avg[1:0] r/w 01 conversion averaging modes. these bits determine the number of conversion results that are collected and averaged before updating the temperature register. the average is an accumulated average and not a running average. table 8 lists the bit settings for avg. 4 t/na r/w 0 therm/alert mode select. 1: therm mode 0: alert mode 3 pol r/w 0 alert pin polarity bit. 1: active high 0: active low 2 dr/alert r/w 0 data ready, alert flag select bit. 1: alert pin reflects the status of the data ready flag 0: alert pin reflects the status of the alert flags 1 soft_reset r/w 0 software reset bit. when set to 1 it triggers software reset with a duration of 2ms this bit always read back 0 0 ? r 0 not used advance information
25 TMP117 www.ti.com snosd82 ? june 2018 product folder links: TMP117 submit documentation feedback copyright ? 2018, texas instruments incorporated table 7. conversion cycle time in cc mode conv[2:0] avg[1:0] = 00 avg[1:0] = 01 000 15.5 ms 125 ms 001 125 ms 125 ms 010 250 ms 250 ms 011 500 ms 500 ms 100 1 s 1 s 101 4 s 4 s 110 8 s 8 s 111 16 s 16 s table 8. avg bit settings avg1 avg0 description 0 0 no averaging,15.5-ms active conversion time 0 1 8 averages, 125-ms active conversion time advance information
26 TMP117 snosd82 ? june 2018 www.ti.com product folder links: TMP117 submit documentation feedback copyright ? 2018, texas instruments incorporated 7.6.1.3 high limit register (address = 02h) [reset = 6000h] this register is a 16-bit, read/write register that stores the high limit for comparison with the temperature result. one lsb equals 7.8125 m c. the range of the register is 256 c. negative numbers are represented in binary two's complement format. following power-up or a general-call reset, the high-limit register is loaded with the stored value from the eeprom that is set as factory default to 6000h. figure 28. high limit register 15 14 13 12 11 10 9 8 h15 h14 h13 h12 h11 h10 h9 h8 r/w-0 r/w-1 r/w-1 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 7 6 5 4 3 2 1 0 h7 h6 h5 h4 h3 h2 h1 h0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 table 9. high limit register field descriptions bit field type reset description 15:0 h[15:0] r/w 6000h 16-bit, read/write register that stores the high limit for comparison with the temperature result. 7.6.1.4 low limit register (address = 03h) [reset = 8000h] this register is configured as a 16-bit, read/write register that stores the low limit for comparison with the temperature result. one lsb equals 7.8125 m c. the range of the register is 256 c. negative numbers are represented in binary two's complement format. following power-up or reset, the low-limit register is loaded with the stored value from the eeprom that is set in the factory to 8000h. figure 29. low limit register 15 14 13 12 11 10 9 8 l15 l14 l13 l12 l11 l10 l9 l8 r/w-1 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 7 6 5 4 3 2 1 0 l7 l6 l5 l4 l3 l2 l1 l0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 table 10. low limit register field descriptions bit field type reset description 15:0 l[15:0] r/w 8000h 16-bit, read/write register that stores the low limit for comparison with the temperature result. 7.6.1.5 temperature offset register (address = 07h) [reset = 0000h] this 16-bit register is to be used as a user-defined temperature offset register during system calibration. the offset will be added to the temperature result after linearization. it has a same resolution of 7.8125m c and same range of 256 c as the temperature result register. if added result is out of boundary, then the temperature result will show as the maximum or minimum value. this register read-write functionality is similar as the eeprom1 register. figure 30. temperature offset register 15 14 13 12 11 10 9 8 d15 d14 d13 d12 d11 d10 d9 d8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 7 6 5 4 3 2 1 0 d7 d6 d5 d4 d3 d2 d1 d0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 advance information
27 TMP117 www.ti.com snosd82 ? june 2018 product folder links: TMP117 submit documentation feedback copyright ? 2018, texas instruments incorporated table 11. temperature offset register field descriptions bit field type reset description 15:0 d[15:0] r/w 0 this 16-bit register is to be used as a scratch pad by the customer. advance information
28 TMP117 snosd82 ? june 2018 www.ti.com product folder links: TMP117 submit documentation feedback copyright ? 2018, texas instruments incorporated 7.6.1.6 eeprom unlock register (address = 04h) [reset = 0000h] figure 31. eeprom unlock register 15 14 13 12 11 10 9 8 eun eeprom_busy ? ? ? ? ? ? r/w-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 7 6 5 4 3 2 1 0 ? ? ? ? ? ? ? ? r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 table 12. eeprom unlock register field descriptions bit field type reset description 15 eun r/w 0 eeprom unlock. 0: eeprom is locked for programming: writes to all eeprom addresses (such as configuration, limits, and eeprom locations 1-4) are written to registers in digital logic and are not programmed in the eeprom 1: eeprom unlocked for programming: any writes to writable registers program the respective location in the eeprom 14 eeprom_busy r 0 eeprom busy. this flag is the mirror of the eeprom busy flag (bit 12) in the configuration register. 0: indicates that the eeprom is ready, which means that the eeprom has finished the last transaction and is ready to accept new commands 1: indicates that the eeprom is busy, which means that the eeprom is currently completing a program or power-up on reset load 13:0 ? r 0 not used 7.6.1.7 eeprom1 register (address = 05h) [reset = 0000h] the eeprom1 register is a 16-bit register that be used as a scratch pad by the customer to store general- purpose data. this register has a corresponding eeprom location. writes to this address when the eeprom is locked write data into the register and not to the eeprom. writes to this register when the eeprom is unlocked causes the corresponding eeprom location to be programmed. see the programming the eeprom section for more information. eeprom[4:1] are preprogrammed during manufacturing with the unique id that can be overwritten. to support nist traceability, do not delete or reprogram eeprom[4:1]. figure 32. eeprom1 register 15 14 13 12 11 10 9 8 d15 d14 d13 d12 d11 d10 d9 d8 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x 7 6 5 4 3 2 1 0 d7 d6 d5 d4 d3 d2 d1 d0 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x table 13. eeprom1 register field descriptions bit field type reset description 15:0 d[15:0] r/w xxxxh this 16-bit register is to be used as a scratch pad by the customer. advance information
29 TMP117 www.ti.com snosd82 ? june 2018 product folder links: TMP117 submit documentation feedback copyright ? 2018, texas instruments incorporated 7.6.1.8 eeprom2 register (address = 06h) [reset = 0000h] this register function the same as the eeprom1 register. figure 33. eeprom2 register 15 14 13 12 11 10 9 8 d15 d14 d13 d12 d11 d10 d9 d8 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x 7 6 5 4 3 2 1 0 d7 d6 d5 d4 d3 d2 d1 d0 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x table 14. eeprom2 register field descriptions bit field type reset description 15:0 d[15:0] r/w xxxxh this 16-bit register is to be used as a scratch pad by the customer. advance information
30 TMP117 snosd82 ? june 2018 www.ti.com product folder links: TMP117 submit documentation feedback copyright ? 2018, texas instruments incorporated 7.6.1.9 eeprom3 register (address = 08h) [reset = xxxxh] this register function is the same as the eeprom1 register. figure 34. eeprom3 register 15 14 13 12 11 10 9 8 d15 d14 d13 d12 d11 d10 d9 d8 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x 7 6 5 4 3 2 1 0 d7 d6 d5 d4 d3 d2 d1 d0 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x table 15. eeprom3 register field descriptions bit field type reset description 15:0 d[15:0] r/w xxxxh this 16-bit register is to be used as a scratch pad by the customer. 7.6.1.10 device id register (address = 0fh) [reset = x116h] this read-only register indicates the device id. figure 35. device id register 15 14 13 12 11 10 9 8 ? ? ? ? did11 did10 did9 did8 r-x r-x r-x r-x r-0 r-0 r-0 r-1 7 6 5 4 3 2 1 0 did7 did6 did5 did4 did3 did2 did1 did0 r-0 r-0 r-0 r-1 r-0 r-1 r-1 r-0 table 16. device id register field descriptions bit field type reset description 15:12 ? r x not used. 11:0 did[11:0] r 116h these bits indicate the device id. advance information
31 TMP117 www.ti.com snosd82 ? june 2018 product folder links: TMP117 submit documentation feedback copyright ? 2018, texas instruments incorporated 8 application and implementation note information in the following applications sections is not part of the ti component specification, and ti does not warrant its accuracy or completeness. ti ? s customers are responsible for determining suitability of components for their purposes. customers should validate and test their design implementation to confirm system functionality. 8.1 application information the TMP117 is used to measure the temperature of the board location where the device is mounted. the programmable address options allow up to four locations on the board to be monitored on a single serial bus. for more information, refer to the related tmp116 ambient air temperature measurement (snoa966), replacing resistance temperature detectors with the tmp116 temp sensor (snoa969), and temperature sensors: pcb guidelines for surface mount devices (snoa967) application reports on ti.com. 8.1.1 typical application note: the sda and alert pins require pullup resistors. figure 36. typical connections 8.1.1.1 design requirements the TMP117 operates only as a slave device and communicates with the host through the i 2 c-compatible serial interface. scl is the input pin, sda is a bidirectional pin, and alert is the output. the TMP117 requires a pullup resistor on the scl, sda, and alert pins. the recommended value for the pullup resistors is 5 k . in some applications the pullup resistor can be lower or higher than 5 k . a 0.1- f bypass capacitor is recommended to be connected between v+ and gnd. an scl pullup resistor is required if the system microprocessor scl pin is open-drain. use a ceramic capacitor type with a temperature rating from ? 40 c to +125 c, placed as close as possible to the v+ pin of the TMP117. the decoupling capacitor reduces any noise induced by the system. when connected directly to gnd, v+, sda, and scl, use the add0 pin for address selection for configuring four possible unique slave id addresses. table 1 explains the addressing scheme. the alert output pin can be connected to a microcontroller interrupt that triggers an event that occurred when the temperature limit exceeds the programmable value in registers 02h and 03h. the alert pin can be left floating if not in use or connected to ground. advance information 5 k 5 k 5 k TMP117 sda scl v+ gnd add0 alert 1 2 3 4 5 6 2-wire interface smbus, i2c compatible controller scl sda int gnd 1.9 v to 3.6 v 0.1 ? f gnd copyright ? 2017, texas instruments incorporated
32 TMP117 snosd82 ? june 2018 www.ti.com product folder links: TMP117 submit documentation feedback copyright ? 2018, texas instruments incorporated application information (continued) 8.1.1.2 detailed design procedure 8.1.1.2.1 TMP117 design procedure the TMP117 is a local temperature sensor. measuring a temperature point with a surface-mount device is very challenging because of the external influence of surrounding air and other components. the TMP117 mainly monitors the pcb temperature at the desired hotspot. to maintain accuracy in applications that requires surface temperature measurement, follow good layout techniques (such as understanding the dominant thermal path, isolating the island surround by the package, and keeping the distance as far as possible from the heat source). for sensors in plastic packages (such as the TMP117 dfn device), figure 37 shows that the die attach pad (dap) provides the most dominant thermal path. with the dap, a board-mounted sensor usually does an excellent job of measuring board temperature. the die sits on top of the metal plate leadframe with a non- conductive die adhesive in between, allowing for a fast thermal response. figure 37. wson package cross section most power-hungry electronic components such as processor chips, field programmable gate arrays (fpgas), application-specific integrated circuits (asics), and voltage regulators heat up during operation. in order to accurately measure the ambient temperature of a sensor in a plastic package, isolate the sensor from the heat source using isolation island techniques and distance. ti recommends two vias per TMP117 dimension of the thermal pad. the dap and two vias help improve thermal characteristics. thus, in order to take advantage of this feature, mount the TMP117 on the board with the two copper planes on the top and bottom of the via of equal length as the exposed die attach dimension. the bottom plane contains the temperature sensing elements. in order to achieve the fast temperature response, the mini board dimension must be enough to accommodate the TMP117 and the bypass capacitor with the isolation air gap to prevent the heat source dissipated to the mini sub- board. 8.1.1.2.2 noise and averaging the device temperature sampling distribution (without internal averaging) covers an area of approximately six neighboring codes. the noise area of the six codes remains the same at full supply and full temperature range with a standard deviation of approximately 1 lsb. the device provides an averaging tool for 8, 32, and 64 samples. as illustrated in , even the 8-sample averaging reduces the internal noise distribution to a theoretical minimum of 2 lsb. this averaging means that if the system temperature slowly changes and the supply voltage is stable, then the 8-sample averaging can be enough to neutralize the device noise and provide stable temperature readings. however, if the system temperature is noisy (such as when measuring air flow temperatures), than higher averaging numbers are recommended to be used. die package pin bond wire epoxy exposed pad . heat flow advance information
33 TMP117 www.ti.com snosd82 ? june 2018 product folder links: TMP117 submit documentation feedback copyright ? 2018, texas instruments incorporated application information (continued) 8.1.1.2.3 self-heating effect (she) during adc conversion some power is dissipated that heats the device despite the small power consumption of the TMP117. consider the self-heating effect (she) for certain precise measurements. figure 38 shows the device she in still air at 25 c after the supply is switched on. the device package, including the thermal pad, is soldered to the 11-mm 20-mm 1.1-mm size coupon board. the board is located horizontally, with the device on top. the TMP117 is in continuous conversion mode with 64 sampling averaging and zero conversion cycle time. there is no digital bus activity aside from reading temperature data one time each second. as shown in figure 38 , the she stabilization time in still air is greater when the device dissipates more power. figure 38. self-heating in still air vs. temperature and dissipated power the she drift is strongly proportional to the device dissipated power. the she drift is also proportional to the device temperature because the consumption current with the same supply voltage increases with temperature. figure 39 shows the she drifts versus temperature and dissipated power at 25 c for the same coupon board and the same conditions described previously. figure 39. self-heating in still air vs. temperature and dissipated power at 25 c to estimate the she for similar size boards, calculate the device consumption power for 25 c and use the corresponding power line shown in figure 39 . for example, in cc mode without dc at a 3.3-v supply at 25 c, the device dissipates 410 wt. so self-heating in still air is approximately 40 m c for the described condition. temperature ( q c) self-heating (mc) -50 -25 0 25 50 75 100 125 150 175 0 10 20 30 40 50 60 70 80 90 700 uwt 630 uwt 500 uwt 410 uwt 370 uwt 225 uwt time (sec) temperature change (mc) 0 10 20 30 40 50 60 70 80 90 0 10 20 30 40 50 d014 1.9 v 3 v advance information
34 TMP117 snosd82 ? june 2018 www.ti.com product folder links: TMP117 submit documentation feedback copyright ? 2018, texas instruments incorporated application information (continued) the following methods can reduce the she: ? system calibration removes not only the self-heating error and power-supply rejection ratio (psrr) effect but also compensates the temperature shift caused by the thermal resistance between the device and the measured object. ? if practical, use the device one-shot mode. if continuous conversion is needed, use the conversion cycle mode with significant standby time. for example, in most cases an 8-sample averaging (125 ms) with a 1- second conversion cycle provides enough time for the device to cool down to the environment temperature and removes the she. ? use the minimal acceptable power supply voltage. ? use a printed-circuit board (pcb) layout that provides minimal thermal resistance to the device. ? avoid using small-value pullup resistors on the sda and alert pins. instead, use pullup resistors larger than 2 k . ? ensure that the scl and sda signal levels remain below 10% or above 90% of the device supply voltage. ? avoid heavy bypass traffic on the data line. communication to other devices on the same data line increases the supply current even if the device is in sd mode. ? use the highest available communication speed. 8.1.1.2.4 synchronized temperature measurements when four temperature measurements are needed in four different places simultaneously, triggering a reset is recommended. in this method, four devices are programed with control registers set to cc mode with a conversion cycle time of 16 s. all four devices are connected to same two-wire bus with four different bus addresses. the bus general-call reset command is issued by the master. this command triggers all devices to reset (which takes approximately 1.5 ms) and triggers a simultaneous temperature sampling according to configuration registers setting. the master has 16 seconds to read data from the devices. advance information
35 TMP117 www.ti.com snosd82 ? june 2018 product folder links: TMP117 submit documentation feedback copyright ? 2018, texas instruments incorporated application information (continued) 8.1.1.3 application curve figure 40 shows how fast the TMP117 reacts to changes in temperature. two elements must be considered when conducting the thermal responses experiment: the thermal conductivity and thermal mass. thermal conductivity is the measure of the capacity of a material (such as still air or stirred oil) to conduct heat. thermal conductivity is mainly used to describe how heat is conducted through a material. higher values reflect greater efficiency of transferring heat. a good layout technique is to keep the thermal mass as small as possible. smaller thermal masses result in better thermal responses. the purpose of these experiments is to investigate how much time is required for the TMP117 temperature to reach the set point temperature and stabilize. there are three types of tests for the thermal response: still air, moving air, and stirred oil, as shown in figure 40 . this figure shows the step response of the TMP117 enclosed in a chamber of still air, in a wind tunnel of moving air, and submerged in an oil bath (for the respective traces) in a temperature environment of 70 c from room temperature (23 c). the time-constant, or the time for the output to reach 63% of the input step is dependent on the type of test. the time-constant result depends on the pcb and the thickness of the board that the TMP117 is mounted to. for this test, the TMP117evm is used to perform the thermal response. the TMP117evm dimension is 7.6 mm 17.8 mm with a 1-mm thickness. among all methods, still air has the slowest thermal response because of the enclosed box placed inside the oven chamber without any helping elements, whereas the stirred oil experiment yields the fastest thermal response time. v+ = 3.3 v, t initial = 23 c, t final = 70 c figure 40. thermal response time (seconds) percent of (final - initial) value ( ) 0.001 0.01 0.1 1 1015 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 stirred oil moving air still air advance information
36 TMP117 snosd82 ? june 2018 www.ti.com product folder links: TMP117 submit documentation feedback copyright ? 2018, texas instruments incorporated 9 power supply recommendations the TMP117 operates on a power-supply range from 1.9 v to 5.5 v. the device is trimmed for operation at a 3.3-v supply, but can measure temperature accurately in the full supply range. a power-supply bypass capacitor is required, which must be placed as close to the supply and ground pins of the device as possible. a typical value for this supply bypass capacitor is 100 nf. applications with noisy or high-impedance power supplies may require additional decoupling capacitors to reject power-supply noise. the TMP117 is a very low-power device that generates low noise on the supply bus. the user can apply an rc filter to the v+ pin of the device to further reduce noise that the TMP117 might propagate to other components. r f in figure 41 must be less than 0.5 k ? and c f must be at least 100 nf. the package thermal pad is not connected to the device ground and can be left floating for convenience or grounded for better thermal resistance. figure 41. noise-reduction techniques 10 layout 10.1 layout guidelines note to achieve a high-precision temperature reading for a rigid pcb, do not solder down the thermal pad. for a flexible pcb, the user can solder the thermal pad to increase board level reliability. for more information on board layout, refer to the related precise temperature measurements with tmp116 (snoa986) and wearable temperature sensing layout considerations optimized for thermal response (snia021) application reports on ti.com. place the power-supply bypass capacitor as close as possible to the supply and ground pins. the recommended value of this bypass capacitor is 0.1 f. additional decoupling capacitance can be added to compensate for noisy or high-impedance power supplies. in some cases, the pullup resistor can be the heat source, therefore, maintain some distance between the resistor and the device. mount the TMP117 on the pcb pad to provide the minimum thermal resistance to the measured object surface or to the surrounding air. the recommended pcb layout minimizes the device self-heating effect, reduces the time delay as temperature changes, and minimizes the temperature offset between the device and the object. ti device scl sda gnd v+ alert add0 c f 100 nf 0.5 k 1.9 v to 3.6 v copyright ? 2017, texas instruments incorporated advance information
37 TMP117 www.ti.com snosd82 ? june 2018 product folder links: TMP117 submit documentation feedback copyright ? 2018, texas instruments incorporated 10.2 layout example figure 42. layout recommendation via to power or ground plane via to internal layer 0.1 f 1 6 sda v+ add0 alert gnd scl 5 4 2 3 exposed thermal pad 5 k 5 k 5 k 1.9 v to 3.6 v i2c bus mcu int advance information
38 TMP117 snosd82 ? june 2018 www.ti.com product folder links: TMP117 submit documentation feedback copyright ? 2018, texas instruments incorporated 11 device and documentation support 11.1 documentation support 11.1.1 related documentation for related documentation see the following: ? tmpx75 temperature sensor with i 2 c and smbus interface in industry standard lm75 form factor and pinout (sbos288) ? tmp275 0.5 c temperature sensor with i2c and smbus interface in industry standard lm75 form factor and pinout (sbos363) ? tmp116 ambient air temperature measurement (snoa966) ? replacing resistance temperature detectors with the tmp116 temp sensor (snoa969) ? temperature sensors: pcb guidelines for surface mount devices (snoa967) ? precise temperature measurements with tmp116 (snoa986) ? wearable temperature sensing layout considerations optimized for thermal response (snia021) 11.2 receiving notification of documentation updates to receive notification of documentation updates, navigate to the device product folder on ti.com. in the upper right corner, click on alert me to register and receive a weekly digest of any product information that has changed. for change details, review the revision history included in any revised document. 11.3 community resources the following links connect to ti community resources. linked contents are provided "as is" by the respective contributors. they do not constitute ti specifications and do not necessarily reflect ti's views; see ti's terms of use . ti e2e ? online community ti's engineer-to-engineer (e2e) community. created to foster collaboration among engineers. at e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. design support ti's design support quickly find helpful e2e forums along with design support tools and contact information for technical support. 11.4 trademarks e2e is a trademark of texas instruments. smbus is a trademark of intel corporation. all other trademarks are the property of their respective owners. 11.5 electrostatic discharge caution this integrated circuit can be damaged by esd. texas instruments recommends that all integrated circuits be handled with appropriate precautions. failure to observe proper handling and installation procedures can cause damage. esd damage can range from subtle performance degradation to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 11.6 glossary slyz022 ? ti glossary . this glossary lists and explains terms, acronyms, and definitions. 12 mechanical, packaging, and orderable information the following pages include mechanical, packaging, and orderable information. this information is the most current data available for the designated devices. this data is subject to change without notice and revision of this document. for browser-based versions of this data sheet, refer to the left-hand navigation. advance information
package option addendum www.ti.com 30-jun-2018 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples pTMP117aidrvr active wson drv 6 3000 tbd call ti call ti -55 to 150 (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) rohs: ti defines "rohs" to mean semiconductor products that are compliant with the current eu rohs requirements for all 10 rohs substances, including the requirement that rohs substance do not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, "rohs" products are suitable for use in specified lead-free processes. ti may reference these types of products as "pb-free". rohs exempt: ti defines "rohs exempt" to mean products that contain lead but are compliant with eu rohs pursuant to a specific eu rohs exemption. green: ti defines "green" to mean the content of chlorine (cl) and bromine (br) based flame retardants meet js709b low halogen requirements of <=1000ppm threshold. antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.
generic package view images above are just a representation of the package family, actual package may vary. refer to the product data sheet for package details. drv 6 wson - 0.8 mm max height plastic small outline - no lead 4206925/f
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